/* Copyright 2007-2008, Unpublished Work of Technologic Systems
 * All Rights Reserved.
 *
 * THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
 * PROPRIETARY AND TRADE SECRET INFORMATION OF TECHNOLOGIC SYSTEMS.
 * ACCESS TO THIS WORK IS RESTRICTED TO (I) TECHNOLOGIC SYSTEMS 
 * EMPLOYEES WHO HAVE A NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE
 * OF THEIR ASSIGNMENTS AND (II) ENTITIES OTHER THAN TECHNOLOGIC
 * SYSTEMS WHO HAVE ENTERED INTO APPROPRIATE LICENSE AGREEMENTS.  NO
 * PART OF THIS WORK MAY BE USED, PRACTICED, PERFORMED, COPIED, 
 * DISTRIBUTED, REVISED, MODIFIED, TRANSLATED, ABRIDGED, CONDENSED, 
 * EXPANDED, COLLECTED, COMPILED, LINKED, RECAST, TRANSFORMED, ADAPTED
 * IN ANY FORM OR BY ANY MEANS, MANUAL, MECHANICAL, CHEMICAL, 
 * ELECTRICAL, ELECTRONIC, OPTICAL, BIOLOGICAL, OR OTHERWISE WITHOUT
 * THE PRIOR WRITTEN PERMISSION AND CONSENT OF TECHNOLOGIC SYSTEMS.
 * ANY USE OR EXPLOITATION OF THIS WORK WITHOUT THE PRIOR WRITTEN
 * CONSENT OF TECHNOLOGIC SYSTEMS COULD SUBJECT THE PERPETRATOR TO
 * CRIMINAL AND CIVIL LIABILITY.
 */

module ts_sdcore(
  wb_clk_i,
  wb_rst_i,

  wb1_cyc_i,
  wb1_cti_i,
  wb1_bte_i,
  wb1_stb_i,
  wb1_we_i,
  wb1_adr_i,
  wb1_dat_i,
  wb1_sel_i,
  wb1_dat_o,
  wb1_ack_o,

  wb2_cyc_i,
  wb2_stb_i,
  wb2_cti_i,
  wb2_bte_i,
  wb2_we_i,
  wb2_adr_i,
  wb2_dat_i,
  wb2_sel_i,
  wb2_dat_o,
  wb2_ack_o,

  wb3_cyc_i,
  wb3_stb_i,
  wb3_cti_i,
  wb3_bte_i,
  wb3_we_i,
  wb3_adr_i,
  wb3_dat_i,
  wb3_sel_i,
  wb3_dat_o,
  wb3_ack_o,

  wb4_cyc_i,
  wb4_stb_i,
  wb4_cti_i,
  wb4_bte_i,
  wb4_we_i,
  wb4_adr_i,
  wb4_dat_i,
  wb4_sel_i,
  wb4_dat_o,
  wb4_ack_o,

  sd_clk_o,
  sd_cmd_o,
  sd_cmd_i,
  sd_cmd_oe_o,
  sd_dat_o,
  sd_dat_i,
  sd_dat_oe_o,
  sd_power_o,
  sd_detect_i,
  sd_wprot_i,
  sd_busy_o,
  sd_lun_o

);

input wb_clk_i, wb_rst_i;

input wb1_cyc_i, wb1_stb_i, wb1_we_i;
input [3:0] wb1_sel_i;
input [31:0] wb1_adr_i, wb1_dat_i;
output [31:0] wb1_dat_o;
output wb1_ack_o;
input [2:0] wb1_cti_i;
input [1:0] wb1_bte_i;

input wb2_cyc_i, wb2_stb_i, wb2_we_i;
input [3:0] wb2_sel_i;
input [31:0] wb2_adr_i, wb2_dat_i;
output [31:0] wb2_dat_o;
output wb2_ack_o;
input [2:0] wb2_cti_i;
input [1:0] wb2_bte_i;

input wb3_cyc_i, wb3_stb_i, wb3_we_i;
input [3:0] wb3_sel_i;
input [31:0] wb3_adr_i, wb3_dat_i;
output [31:0] wb3_dat_o;
output wb3_ack_o;
input [2:0] wb3_cti_i;
input [1:0] wb3_bte_i;

input wb4_cyc_i, wb4_stb_i, wb4_we_i;
input [3:0] wb4_sel_i;
input [31:0] wb4_adr_i, wb4_dat_i;
output [31:0] wb4_dat_o;
output wb4_ack_o;
input [2:0] wb4_cti_i;
input [1:0] wb4_bte_i;

output [7:0] sd_clk_o;
output sd_cmd_o, sd_cmd_oe_o, sd_power_o;
output [3:0] sd_dat_o;
output [3:0] sd_dat_oe_o;
input sd_cmd_i;
input [7:0] sd_wprot_i, sd_detect_i;
input [3:0] sd_dat_i;
output sd_busy_o;
output [2:0] sd_lun_o;

parameter multicard = 1'b0;

endmodule
