/* Copyright 2012-2013. Unpublished Work of Technologic Systems.
 * All Rights Reserved.
 *
 * THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
 * PROPRIETARY AND TRADE SECRET INFORMATION OF TECHNOLOGIC SYSTEMS.
 * ACCESS TO THIS WORK IS RESTRICTED TO (I) TECHNOLOGIC SYSTEMS 
 * EMPLOYEES WHO HAVE A NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE
 * OF THEIR ASSIGNMENTS AND (II) ENTITIES OTHER THAN TECHNOLOGIC
 * SYSTEMS WHO HAVE ENTERED INTO APPROPRIATE LICENSE AGREEMENTS.  NO
 * PART OF THIS WORK MAY BE USED, PRACTICED, PERFORMED, COPIED, 
 * DISTRIBUTED, REVISED, MODIFIED, TRANSLATED, ABRIDGED, CONDENSED, 
 * EXPANDED, COLLECTED, COMPILED, LINKED, RECAST, TRANSFORMED, ADAPTED
 * IN ANY FORM OR BY ANY MEANS, MANUAL, MECHANICAL, CHEMICAL, 
 * ELECTRICAL, ELECTRONIC, OPTICAL, BIOLOGICAL, OR OTHERWISE WITHOUT
 * THE PRIOR WRITTEN PERMISSION AND CONSENT OF TECHNOLOGIC SYSTEMS.
 * ANY USE OR EXPLOITATION OF THIS WORK WITHOUT THE PRIOR WRITTEN
 * CONSENT OF TECHNOLOGIC SYSTEMS COULD SUBJECT THE PERPETRATOR TO
 * CRIMINAL AND CIVIL LIABILITY.
 */

module wb_dpram_32kbyte(
  wb_clk_i,
  wb_rst_i,

  wb1_adr_i,
  wb1_dat_i,
  wb1_dat_o,
  wb1_cyc_i,
  wb1_stb_i,
  wb1_ack_o,
  wb1_we_i,
  wb1_sel_i,

  wb2_adr_i,
  wb2_dat_i,
  wb2_dat_o,
  wb2_cyc_i,
  wb2_stb_i,
  wb2_ack_o,
  wb2_sel_i,
  wb2_we_i
);

input wb_clk_i, wb_rst_i;
input [31:0] wb1_adr_i, wb2_adr_i;
input [31:0] wb1_dat_i, wb2_dat_i;
input wb1_cyc_i, wb2_cyc_i, wb1_stb_i, wb2_stb_i, wb1_we_i, wb2_we_i;
input [3:0] wb1_sel_i, wb2_sel_i;
output [31:0] wb1_dat_o, wb2_dat_o;
output wb1_ack_o, wb2_ack_o;

reg ack1, ack2;
reg [3:0] we1, we2;

assign wb1_ack_o = ack1;
assign wb2_ack_o = ack2;

always @(posedge wb_rst_i or posedge wb_clk_i) begin
  if (wb_rst_i) begin
    ack1 <= 1'b0;
    ack2 <= 1'b0;
    we1 <= 4'h0;
    we2 <= 4'h0;
  end else begin
    ack1 <= wb1_cyc_i && wb1_stb_i && !ack1;
    ack2 <= wb2_cyc_i && wb2_stb_i && !ack2;
    we1 <= 4'h0;
    we2 <= 4'h0;
    if (wb1_cyc_i && wb1_stb_i && wb1_we_i && !ack1) we1 <= wb1_sel_i;
    if (wb2_cyc_i && wb2_stb_i && wb2_we_i && !ack2) we2 <= wb2_sel_i;
  end
end

blockram_8kx4byte blockram0 (
  .clka(wb_clk_i),
  .wea(we1),
  .addra(wb1_adr_i[14:2]),
  .dina(wb1_dat_i),
  .douta(wb1_dat_o),
  .clkb(wb_clk_i),
  .web(we2),
  .addrb(wb2_adr_i[14:2]),
  .dinb(wb2_dat_i),
  .doutb(wb2_dat_o)
);

endmodule

